The present disclosure relates to a semiconductor device having a multilayer structure and a method for manufacturing the semiconductor device.
In trends of semiconductor miniaturization, attention has recently been directed to a beyond-Moore approach, which stacks elements in a vertical direction with respect to a substrate and connects wiring three-dimensionally, in place of a more-Moore approach aimed at a higher degree of integration by further miniaturization in mask processes.
Lamination in a three-dimensional direction can reduce RC between elements, and enables cost reduction when the development of package technology at a wafer level makes progress.
For example, Japanese Patent Laid-Open No. Hei 11-261000 discloses first forming buried wiring in a wafer of a first layer and exposing the buried wiring by grinding a Si substrate after ending a wafer process. Then, bumps are formed on the exposed wiring, and the wafer of the first layer is laminated to a wafer of a second layer which wafer is fabricated in a similar manner. An electric connection between the first layer and the second layer is established via the bumps.
In addition, “A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor,” Suntharalingam, V.; Berger, R.; Clark, S.; Knecht, J.; Messier, A.; Newcomb, K.; Rathman, D.; Slattery, R.; Soares, A.; Stevenson, C.; Warner, K.; Young, D.; Lin Ping Ang; Mansoorian, B.; Shaver, D.; ISSCC 2009, discloses a method that makes a hole so as to be in contact with or penetrate a conductive pad section provided in advance within each of wafers after laminating circuits to each other, and establishes an electric connection between the wafers by burying a conductive material in the hole.
Some semiconductor devices have a structure referred to as a seal ring or a guard ring formed in a peripheral section of a chip in order to prevent damage to the devices due to cracks occurring when the semiconductor devices are divided into individual pieces or prevent the intrusion of water from side surfaces into the devices.
A seal ring is for example composed of wiring in a multilayer wiring region formed by alternately disposing insulating layers and wiring layers on a semiconductor element and a connecting part for connecting each of these pieces of wiring, the connecting part penetrating the interlayer insulating films.
For example, Japanese Patent Laid-Open No. 2006-140404 discloses disposing a seal ring in a wiring layer and forming a groove penetrating a protective film and reaching a position between a low dielectric constant film and the protective film on the outside of the seal ring. This is intended to prevent the development of cracks occurring when a wafer of a structure including the low dielectric constant interlayer film is diced, by this groove and the seal ring. Peeling at the time of the dicing is purported to be thereby prevented.